Publications
Cite Preesm
Please, use the following reference if you wish to add a reference to Preesm in a scientific publication:
Pelcat, Maxime; Desnos, Karol; Heulot, Julien; Guy, Clément; Nezan, Jean-François; Aridhi Slaheddine (2014) “PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming”. EDERC 2014, Milan, Italy.
@INPROCEEDINGS{
Pelcat\_Preesm\_2014,
author={Pelcat, M. and Desnos, K. and Heulot, J. and Guy, C. and Nezan, J.-F. and Aridhi, S.},
booktitle={Education and Research Conference (EDERC), 2014 6th European Embedded Design in},
title={Preesm: A dataflow-based rapid prototyping framework for simplifying multicore DSP programming},
year={2014},
month={Sept},
pages={36-40},
doi={10.1109/EDERC.2014.6924354}
}
Preesm Related Publications
Books
2012
- Pelcat, Maxime; Aridhi, Slaheddine; Piat, Jonathan; Nezan, Jean-François (2012) “Physical Layer Multicore Prototyping: A Dataflow-Based Approach for LTE eNodeB”. Springer.
Journal Articles
2020
- Suriano, Leonardo, Andrés Otero, Alfonso Rodríguez, Manuel Sánchez-Renedo, and Eduardo de la Torre. “Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs.” IEEE Access (2020).
2019
- Suriano, Leonardo, Florian Arrestier, Alfonso Rodríguez, Julien Heulot, Karol Desnos, Maxime Pelcat, and Eduardo de la Torre. “DAMHSE: Programming Heterogeneous MPSoCs with Hardware Acceleration using Dataflow-Based Design Space Exploration and Automated Rapid Prototyping.” Microprocessors and Microsystems (2019): 102882.
2017
- Ammar, Manel; Baklouti, Mouna; Pelcat, Maxime; Desnos, Karol; Abid, Mohamed (2017) “Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs”. Journal of Signal Processing Systems (JSPS), Springer.
2016
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2016) “On Memory Reuse Between Inputs and Outputs of Dataflow Actors”. Transactions on Embedded Computing Systems (TECS), ACM.
2014
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2014) “Memory analysis and optimized allocation of dataflow applications on shared-memory MPSoCs”. Journal of Signal Processing Systems (JSPS), Springer.
- Zheng, Zhou; Plishker, William; Bhattacharyya, Shuvra S.; Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François (2014) “Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing”. Journal of Signal Processing Systems (JSPS), Springer.
2009
- Pelcat, Maxime; Piat, Jonathan; Wipliez, Matthieu; Aridhi, Slaheddine; Nezan, Jean-François (2009). “An Open Framework for Rapid Prototyping of Signal Processing Applications“. EURASIP Journal on Embedded Systems.
Conference and Workshop papers
2020
- Suriano, Leonardo, David Lima, and Eduardo de la Torre. “Accelerating a Classic 3D Video Game on Heterogeneous Reconfigurable MPSoCs.” International Symposium on Applied Reconfigurable Computing. Springer, Cham, 2020. Open-Source Files and Instructions can be found here.
2018
- Miomandre, Hugo; Hascoët, Julien; Desnos, Karol; Martin, Kevin; Dinechin, Benoît Dupont De; Nezan, Jean-François (2018). “Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures“. PARMA-DITAM.
- Madroñal, Daniel; Lazcano, Raquel; Morvan, Antoine; Salvador, Ruben; Desnos, Karol; Juarez, Eduardo; Sanz, Cesar (2018). “Automatic Instrumentation of Dataflow Application using PAPI Inproceedings Forthcoming“. Computing Frontiers.
- Arrestier, Florian; Desnos, Karol; Pelcat, Maxime; Heulot, Julien; Eduardo, Juarez; Daniel, Menard (2018). “Delays and States in Dataflow Models of Computation Inproceedings Forthcoming“. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS).
2017
- Deroui, Hamza; Desnos, Karol; Nezan, Jean-François; Munier-Kordon, Alix (2017) “Throughput Evaluation of DSP Applications based on Hierarchical Dataflow Models”. ISCAS 2017, Baltimore, MD, USA.
- Deroui, Hamza; Desnos, Karol; Nezan, Jean-François; Munier-Kordon, Alix (2017) “Relaxed Subgraph Execution Model for the Throughput Evaluation of IBSDF Graphs”. SAMOS 2017, Samos, Greece.
- Hascoet, Julien; Desnos, Karol; Nezan, Jean-François; Dupont de Dinechin, Benoit (2017) “Hierarchical Dataflow Model for Efficient Programming of Clustered Manycore Processors”. ASAP2017, Seattle, WA, USA.
- Suriano, Leonardo; Rodriguez, Alfonso; Desnos, Karol; Pelcat, Maxime; de La Torre, Eduardo (2017) “Analysis of Heterogeneous Multi-Core Multi-HW Accelerator Based Systems Designed Using PREESM and SDSoC”. ReCoSoC 2017, Madrid, Spain.
- Georgakarakos, Georgios; Kanur, Sudeep; Lilius, Johan; Desnos, Karol (2017) “Task-based Execution of Synchronous Dataflow Graphs for Scalable Multicore Computing”. SiPS 2017, Lorient, France.
- Kanur, Sudeep; Lilius, Johan; Ersfolk, Johan (2017) “Detecting Data-Parallel Synchronous Dataflow Graphs”. DASIP 2017, Dresden, Germany.
2016
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2016) “Distributed Memory Allocation Technique for Synchronous Dataflow Graphs”. SiPS 2016, Dallas, TX, USA.
- Pelcat, Maxime; Desnos Karol; Maggiani, Luca; Liu, Yanzhou; Heulot, Julien; Nezan, Jean-François; Bhattacharyya, Suhvra S. (2016) “Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems”. SiPS 2016, Dallas, TX, USA.
- Ammar, Manel; Baklouti, Mouna; Pelcat, Maxime; Desnos, Karol; Abid, Mohamed (2015) “On Exploiting Energy-Aware Scheduling Algorithms for MDE-based Design Space Exploration of MP2SoC”. PDP 2016, Heraklion Crete, Greece.
2015
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2015) “Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications”. ICASSP 2015, Brisbane, Australia.
- Ammar, Manel; Baklouti, Mouna; Pelcat, Maxime; Desnos, Karol; Abid, Mohamed (2015) “Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems”. SNPD 2015, Takamatsu, Japan.
2014
- Ammar, Manel; Baklouti, Mouna; Pelcat, Maxime; Desnos, Karol; Abid, Mohamed (2014) “MARTE to PiSDF transformation for data-intensive applications analysis”. DASIP 2014, Madrid, Spain.
- Desnos, Karol; El Assad, Safwan; Arlicot, Aurore; Pelcat, Maxime; Menard, Daniel (2014) “Efficient Multicore Implementation of An Advanced Generator of Discrete Chaotic Sequences”. CIHS 2014, London, UK.
- Desnos, Karol; Heulot, Julien (2014) “PiSDF: Parameterized & Interfaced Synchronous Dataflow for MPSoCs Runtime Reconfiguration”. METODO Workshop 2014, Madrid, Spain.
- Heulot, Julien; Menant, Judicaël; Pelcat, Maxime; Nezan, Jean-Francois; Morin, Luce; Pressigout, Muriel; Aridhi, Slaheddine (2014) “Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC on a Stereo Matching Application”. DASIP Conference Demo Night, Madrid, Spain.
- Heulot, Julien; Pelcat, Maxime; Desnos, Karol; Nezan, Jean-François; Aridhi, Slaheddine (2014) “SPIDER: A Synchronous Parameterized and Interfaced Dataflow-Based RTOS for Multicore DSPs”. EDERC 2014, Milan, Italy.
- Heulot, Julien; Pelcat, Maxime; Nezan, Jean-François; Oliva, Yaset; Aridhi, Slaheddine; Bhattacharyya, Shuvra S. (2014) “Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems”. GlobalSIP 2014, Atlanta, USA.
- Holmbacka, Simon; Nogues, Erwan; Pelcat, Maxime; Lafond, Sébastien; Lilius, Johan (2014) “Energy Efficiency and Performance Management of Parallel Dataflow Applications”. DASIP 2014, Madrid, Spain. [Best Paper Award]
- Pelcat, Maxime; Desnos, Karol; Heulot, Julien; Guy, Clément; Nezan, Jean-François; Aridhi Slaheddine (2014) “PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming”. EDERC 2014, Milan, Italy. [2nd Best Paper Award]
2013
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Bhattacharyya, Shuvra S.; Aridhi, Slaheddine (2013) “PiMM: Parameterized and Interfaced Dataflow Meta-Model for MPSoCs Runtime Reconfiguration”. SAMOS XIII, Samos, Greece.
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2013) “Pre- and Post-Scheduling Memory Allocation Strategies on MPSoCs”. ESLSyn13, Austin TX, USA.
- Heulot, Julien; Boutellier, Jani; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2013) “Applying the Adaptive Hybrid Flow-Shop Scheduling Method to Schedule a 3GPP LTE Physical Layer Algorithm onto Many-Core Digital Signal Processors”. AHS, Torino, Italy.
- Heulot, Julien; Oliva, Yaset; Pelcat, Maxime; Nezan, Jean-François; Prevotet, Jean-Christophe (2013) “Dataflow-based Adaptive Multicore Execution on a Xilinx Zynk Platform”. DATE University booth, Grenoble, France.
- Zhou, Zheng; Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Plishker, William; Bhattacharyya, Shuvra (2013) “Scheduling of Parallelized Synchronous Dataflow Actors”. SoC13, Tampere, Finland.
2012
- Desnos, Karol; Pelcat, Maxime; Nezan, Jean-François; Aridhi, Slaheddine (2012) “Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph”. SAMOS Samos.
- Heulot, Julien; Desnos, Karol; Nezan, Jean-François; Pelcat, Maxime; Raulet, Mickaël; Yviquel, Hervé; Lagalaye, Pierre-Laurent; Le Lann, Jean-Christophe (2012) “An Experimental Toolchain Based on High-Level Dataflow Models of Computation For Heterogeneous MPSoC”. DASIP, Karlsruhe, Germany.
2009
- Pelcat, Maxime; Nezan, Jean-François; Piat, Jonathan; Croizer, Jérôme; Aridhi, Slaheddine (2009). “A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems“. DASIP Sophia Antipolis.
- Pelcat, Maxime; Menuet, Pierrick; Aridhi, Slaheddine; Nezan, Jean-François (2009). “Scalable compile-time scheduler for multi-core architectures“. DATE Nice.http://www.see.ed.ac.uk/ahs2013/
- Piat, Jonathan; Bhattacharyya, Shuvra S.; Pelcat, Maxime; Raulet, Mickaël (2009). “Multi-Core Code Generation From Interface Based Hierarchy“. DASIP Sophia Antipolis.
- Piat, Jonathan; Bhattacharyya, Shuvra S.; Raulet, Mickaël (2009). “Interface-based hierarchy for synchronous data-flow graphs“. SiPS Tampere.
Presentations and Tutorials
2017
- Antoine Morvan, Karol Desnos: PREESM Tutorial. CPS School 2017, Alghero, Italy.
2014
- Maxime Pelcat, PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming. EDERC 2014, Milan, Italy.
- Maxime Pelcat, Karol Desnos and Clément Guy, PREESM Tutorial: Dataflow Programming of Multicore DSPs. EDERC 2014, Milan, Italy. [Best Demonstration Award]
PhD Thesis Using Preesm
2016
- Nogues, Erwan (2016) “Energy Optimization of Signal Processing on MPSoCs and its Application to Video Decoding”. PhD Thesis, INSA Rennes, France.
2015
- Heulot, Julien (2015) “Runtime multicore scheduling techniques for dispatching parameterized signal and vision dataflow applications on heterogeneous MPSoCs”. PhD Thesis, INSA Rennes, France.
2014
- Desnos, Karol (2014) “Memory Study and Dataflow Representations for Rapid Prototyping of Signal Processing Applications on MPSoCs”. PhD Thesis, INSA Rennes, France.
2010
- Piat, Jonathan (2010). “Data flow modelling and optimization of loops for multi-core architectures“. PhD Thesis, INSA de Rennes.
- Pelcat, Maxime (2010). “Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs“. PhD Thesis, INSA de Rennes.
Technical Reports
2015
- Pelcat, Maxime; Desnos, Karol; Maggiani, Luca; Liu, Yanzhou; Heulot, Julien; Nezan, Jean-François; Bhattacharyya, Shuvra S. (2015) “Models of Architecture”, Technical Report PREESM/2015-12TR01.
2014
- Pelcat, Maxime; Desnos, Karol; Heulot, Julien; Guy, Clément; Nezan, Jean-François; Aridhi, Slaheddine (2014) ”Dataflow-Based Rapid Prototyping for Multicore DSP Systems”, Technical Report PREESM/2014-05TR01.